An inspection apparatus, which uses an electron beam, irradiates a target semiconductor wafer to be inspected with an electron beam, and detects a secondary electron generated therefrom. The inspection apparatus then creates an image from the detected secondary electron so as to detect a defective semiconductor wafer. In order to create a fine structure image, an electron beam is thinly converged with an electron lens, and the electron beam is then scanned over a semiconductor wafer to acquire a secondary electron image. Next, the-thus detected secondary electron image is compared with a reference image having the same pattern. An area in which the difference between these images is large, or a position at which the difference between these images is large, is judged to be a defect (refer to, for example, Japanese Unexamined Patent Application Publication No. JP05-258703A1).
Since such a method for inspecting the whole surface of a semiconductor wafer requires an extremely long period of time for inspection, it cannot be used for monitoring manufacturing processes. As a measure for such a drawback, a technique for shortening the inspection time is known (refer to, for example, Japanese Unexamined Patent Application Publication No. JP10-089931A1). According to this technique, if a target wafer includes a plurality of patterns in which an area having the two-dimensional repeatability of a semiconductor wafer and an area having the repeatability only in an X direction or a Y direction coexist, a cross comparison is made between an attention point and a comparison point that is apart from the attention point by a repeated pitch. Only an area in which there is the difference from the attention point and the comparison point is extracted as a defect candidate, thereby shortening the inspection time. In addition, noise reduction by a RIA (Reference Image Averaging) technique is also known; the RIA technique averages an image including a defect, and a reference image that does not include a defect (refer to non-patent literature 1 titled “Robust Defect Detection Method Using Reference Image Averaging for High Throughput SEM Wafer Pattern Inspection System” by H. Okuda et al., SPIE Vol. 6152 61524F-1 (2006)).
The number of functions per unit area of a circuit pattern to be inspected by an inspection apparatus has increased four times in the past three years. This increase is achieved by the miniaturization of a pattern. Accordingly, if a defect is minute, it is difficult to discriminate the defect from noises included in a signal of a normal pattern. As a result, it is difficult to make a defect detect that will be achieved when a difference between a defective pattern and a normal pattern is calculated. For example, a memory mat of a memory device is subjected to ultimate pattern miniaturization because one memory cell is assigned to one memory bit for the memory mat. Even if a minute defect on a memory mat cannot be detected, the device normally operates as a whole. The miniaturization of the memory mat is further accelerated by use of the redundant circuit technique. In contrast, if peripheral circuits other than memory mats have one failure in a device, the device will become defective. Therefore, to prevent a defective part relating to peripheral circuits from occurring and to detect defects that may be produced without fail, the pattern size of a peripheral circuit is not so miniaturized in comparison with that of a memory mat. Therefore, when the distribution of positions at which a pattern defect has occurred is referred to, the memory mat is higher in a defect occurrence ratio than the peripheral circuit. In particular, because the pattern density rapidly changes in the most circumferential portion of the memory mat, due to a deviation from the design size at the time of exposure or the like, manufacture of the devices is extremely difficult. As a result, a rate of occurrence of a pattern defect is disadvantageously very high.
Because a die having a plurality of identical patterns is formed on a semiconductor wafer, the conventional inspection apparatuses adopt a die comparison method in which die patterns are compared with each other. The die comparison method has the advantage that the whole die can be subjected to defect judgment. However, because a comparison is made between patterns that are apart from each other by about 10 mm on a wafer and the formed patterns are different from each other, the defect judgment performance may somewhat decrease in the die comparison method.
On the other hand, the conventional inspection apparatuses adopt a cell comparison method in which a comparison is made between patterns that are apart from each other by repeated pitch. This cell comparison method takes advantage of the repeatability of a memory mat. Because the cell comparison method uses the repeatability, the cell comparison method has the disadvantage that a peripheral circuit having no repeatability, and an edge portion of the repetition, cannot be inspected. However, because a comparison is made between areas that are apart from each other only by repeated pitch, the similarity of a pattern is very high, which makes it possible to achieve the defect judgment with high sensitivity. This is the advantage of the cell comparison method. On the other hand, in the cross-comparison method in which comparisons are made in a plurality of directions using the repeatability, inspection is performed on the basis of the repeatability including an area having no repeatability. Therefore, many normal portions each having no repeatability are output as defect candidate points. This requires an image processing system to have high throughput and it cannot be said that sufficient consideration is made in terms of performance. Under these circumstances, although highly sensitive inspection of an area including the most circumferential portion of a memory mat is indispensable, these points are not sufficiently considered for the conventional inspection apparatuses.